This invention relates to a method for designing a semiconductor integrated circuit.
In a layout phase of laying out a net list generated by logically synthesizing, for example, HDL (hardware Description Language) description data in designing a semiconductor integrated circuit, optimization of timing is considered (for example, JP-A 2003-330986 (Kokai))
In the semiconductor integrated circuit, in recent years, the scale thereof has become large and the circuit has become fine, and furthermore, by lowering of the power voltage, IR drop (voltage lowering) has become large, and in the cell layout only considering timing, it is feared that the IR drop varies among the regions in the chip and that the maximum IR drop value becomes large. If the maximum value and the variation of the IR drop in the chip are large, difficulty of design or period for design increases and the circuit operation becomes unstable.